Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
Table 4-18. Bridge Control Register Description (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
0
PERR_EN
RW
Parity error response enable. Controls the bridge's response to data, uncorrectable
address, and attribute errors on the secondary interface. Also, the bridge always forwards
data with poisoning, from conventional PCI to PCIe on an uncorrectable conventional PCI
data error, regardless of the setting of this bit.
address, and attribute errors on the secondary interface. Also, the bridge always forwards
data with poisoning, from conventional PCI to PCIe on an uncorrectable conventional PCI
data error, regardless of the setting of this bit.
0 = Ignore uncorrectable address, attribute, and data errors on the secondary interface
(default)
1 = Enable uncorrectable address, attribute, and data error detection and reporting on
the secondary interface
4.31 PM Capability ID Register
This read-only register identifies the linked list item as the register for PCI power management. The
register returns 01h when read.
register returns 01h when read.
PCI register offset:
50h
Register type:
Read only
Default value:
01h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
1
4.32 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge.
This register reads 80h pointing to the subsystem ID capabilities registers.
This register reads 80h pointing to the subsystem ID capabilities registers.
PCI register offset:
51h
Register type:
Read only
Default value:
60h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
1
1
0
0
0
0
0
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Classic PCI Configuration Space
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