Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
4.42 MSI Message Data Register
This register contains the data that software programmed the bridge to send when it send a MSI message.
See
See
for a complete description of the register contents.
PCI register offset:
6Ch
Register type:
Read/Write
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-24. MSI Message Data Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:4
MSG
RW
System specific message. This field contains the portion of the message that the bridge
forwards unmodified.
forwards unmodified.
3:0
MSG_NUM
RW
Message number. This portion of the message field may be modified to contain the
message number is multiple messages are enable. The number of bits that are modifiable
depends on the number of messages enabled in the message control register.
message number is multiple messages are enable. The number of bits that are modifiable
depends on the number of messages enabled in the message control register.
1 message = No message data bits can be modified (default).
2 messages = Bit 0 can be modified.
4 messages = Bits 1:0 can be modified.
8 messages = Bits 2:0 can be modified.
16 messages = Bits 3:0 can be modified.
2 messages = Bit 0 can be modified.
4 messages = Bits 1:0 can be modified.
8 messages = Bits 2:0 can be modified.
16 messages = Bits 3:0 can be modified.
NOTE
Enabling MSI messaging in the XIO2213B has no effect.
4.43
SSID/SSVID Capability ID Register
This read-only register identifies the linked list item as the register for subsystem ID and subsystem
vendor ID capabilities. The register returns 0Dh when read.
vendor ID capabilities. The register returns 0Dh when read.
PCI register offset:
80h
Register type:
Read only
Default value:
0Dh
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
1
1
0
1
4.44 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge.
This register reads 90h pointing to the PCI Express capabilities registers.
This register reads 90h pointing to the PCI Express capabilities registers.
PCI register offset:
81h
Register type:
Read only
Default value:
90h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
1
0
0
1
0
0
0
0
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Classic PCI Configuration Space
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