Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
Produktcode
XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
4.53 Link Capabilities Register
The link capabilities register indicates the link-specific capabilities of the bridge. See
for a
complete description of the register contents.
PCI register offset:
9Ch
Register type:
Read only
Default value:
0006 XC11h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
x
x
x
1
1
0
0
0
0
0
1
0
0
0
1
Table 4-29. Link Capabilities Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:24
PORT_NUM
R
Port number. This field indicates port number for the PCIe link. This field is read-only 00h
indicating that the link is associated with port 0.
indicating that the link is associated with port 0.
23:19
RSVD
R
Reserved. Return 00 0000b when read.
18
CLK_PM
R
Clock power management. This bit is hardwired to 1 to indicate that XIO2213B supports clock
power management through CLKREQ protocol.
power management through CLKREQ protocol.
17:15
L1_LATENCY
R
L1 exit latency. This field indicates the time that it takes to transition from the L1 state to the L0
state. Bit 6 (CCC) in the link control register (offset A0h, see
state. Bit 6 (CCC) in the link control register (offset A0h, see
) equals 1b for a
common clock and equals 0b for an asynchronous clock.
For a common reference clock, the value of this field is determined by bits 20:18
(L1_EXIT_LAT_ASYNC) of the control and diagnostic register 1 (offset C4h, see
(L1_EXIT_LAT_ASYNC) of the control and diagnostic register 1 (offset C4h, see
For an asynchronous reference clock, the value of this field is determined by bits 17:15
(L1_EXIT_LAT_COMMON) of the control and diagnostic register 1 (offset C4h, see
(L1_EXIT_LAT_COMMON) of the control and diagnostic register 1 (offset C4h, see
14:12
L0S_LATENCY
R
L0s exit latency. This field indicates the time that it takes to transition from the L0s state to the
L0 state. Bit 6 (CCC) in the link control register (offset A0h, see
L0 state. Bit 6 (CCC) in the link control register (offset A0h, see
) equals 1b for a
common clock and equals 0b for an asynchronous clock.
For a common reference clock, the value of 011b indicates that the L1 exit latency falls between
256 ns to less than 512 ns.
256 ns to less than 512 ns.
For an asynchronous reference clock, the value of 100b indicates that the L1 exit latency falls
between 512 ns to less than 1 s.
between 512 ns to less than 1 s.
11:10
ASLPMS
R
Active-state link PM support. This field indicates the level of active-state power management
that the bridge supports. The value 11b indicates support for both L0s and L1 through active-
state power management.
that the bridge supports. The value 11b indicates support for both L0s and L1 through active-
state power management.
9:4
MLW
R
Maximum link width. This field is encoded 00 0001b to indicate that the bridge only supports a
1× PCIe link.
1× PCIe link.
3:0
MLS
R
Maximum link speed. This field is encoded 1h to indicate that the bridge supports a maximum
link speed of 2.5 Gb/s.
link speed of 2.5 Gb/s.
Copyright © 2008–2013, Texas Instruments Incorporated
Classic PCI Configuration Space
77
Product Folder Links: