Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
Produktcode
XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
4.64 PHY Control and Diagnostic Register 2
The contents of this register are used for monitoring status and controlling behavior of the PHY macro for
diagnostic purposes. See
diagnostic purposes. See
for a complete description of the register contents. It is
recommended that all values within this register be left at the default value. Improperly programming fields
in this register may cause interoperability or other problems.
in this register may cause interoperability or other problems.
PCI register offset:
C8h
Register type:
Read/Write
Default value:
3214 2000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-38. Control and Diagnostic Register 2 Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:24
(1)
N_FTS_ ASYNC_
RW
N_FTS for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h,
CLK
see
) is clear, the value in this field is the number of FTS that are sent on a
transition from L0s to L0. This field shall default to 32h.
23:16
(1)
N_FTS_COMMON_
RW
N_FTS for common clock. When bit 6 (CCC) of the link control register (offset A0h, see
CLK
) is set, the value in this field is the number of FTS that are sent on a transition
from L0s to L0. This field defaults to 14h.
15:13
PHY_REV
R
PHY revision number
12:8
(1)
LINK_NUM
RW
Link number
7
EN_L2_PWR_
RW
Enable L2 power savings
SAVE
0 = Power savings not enabled when in L2
1 = Power savings enabled when in L2
1 = Power savings enabled when in L2
6
BAR1_EN
RW
BAR 1 enable
0 = BAR at offset 14h is disabled (default).
1 = BAR at offset 14h is enabled.
1 = BAR at offset 14h is enabled.
5
BAR0_EN
RW
BAR 0 enable
0 = BAR at offset 10h is disabled (default).
1 = BAR at offset 10h is enabled.
1 = BAR at offset 10h is enabled.
4
REQ_RECOVERY
RW
REQ_RECOVERY to LTSSM
3
REQ_RECONFIG
RW
REQ_RECONFIGURE to LTSSM
2
REQ_HOT_RESET
RW
REQ_HOT_RESET to LTSSM
1
REQ_DIS_
RW
REQ_DISABLE_SCRAMBLER to LTSSM
SCRAMBLER
0
REQ_LOOPBACK
RW
REQ_LOOPBACK to LTSSM
(1)
These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
Copyright © 2008–2013, Texas Instruments Incorporated
Classic PCI Configuration Space
87
Product Folder Links: