Texas Instruments MuxIt-EVM Evaluation Module MUXIT-EVM MUXIT-EVM Datenbogen
Produktcode
MUXIT-EVM
Parallel Operation Using Two LVDS Data Pairs
4-9
Operation
Figure 4–4. 8- to 20-Bit Parallel Operation Using Two LVDS Data Lines
Data and Clock Input
Data and Clock Output
GND
GND
GND
GND
GND
GND
VCC
VCC
SN65LVDS150
MuxIt PLL
Frequency Multiplier (U1)
CRI
MCO
+ –
LVO
M1
M2
M3
M4
M5
EN
VT
LCRO
EN
BSEL
LCRO
– +
– +
SN65LVDS150
MuxIt PLL
Frequency Multiplier (U1)
CRI
MCO
+ –
LVO
M1
M2
M3
M4
M5
EN
VT
LCRO
EN
BSEL
LCRO
– +
– +
SN65LVDS151
MuxIt
Serializer–Transmitter (U4)
LVI
+ –
+ –
– +
DI–0 ... DI–9
LCRI
EN
– +
LCO
EN
CI
EN
– +
CI
MCI
LCO
DO
SN65LVDS151
MuxIt
Serializer–Transmitter (U3)
LVI
+ –
+ –
– +
DI–0 ... DI–9
LCRI
EN
– +
LCO
EN
CI
EN
– +
CI
MCI
LCO
DO
SN65LVDS152
MuxIt
Receiver–Deserializer (U2)
LVI
DCO
DO–0 ... DO–9
+ –
+ –
– +
– +
CO
EN
EN
CO
LCI
DI
MCI
SN65LVDS152
MuxIt
Receiver–Deserializer (U4)
LVI
DCO
DO–0 ... DO–9
+ –
+ –
– +
– +
CO
EN
EN
CO
LCI
DI
MCI
T*
T*
T*
T*
T*
T*
NOTE: U2 in the Serializer and U3 in the Deserializer are not shown
LVDS Serial Link,
2 Data + 1 Clock
The user may notice that when implementing basic operation, the minimum
number of parallel bits is four, which corresponds to the lowest PLL clock
multiplier ratio. This minimum number is increased by the number of LVDS
pairs used in parallel operation. The MuxIt EVM uses two serializer-transmit-
ters and two LVDS pairs, which doubles the minimum number of data bits (four
number of parallel bits is four, which corresponds to the lowest PLL clock
multiplier ratio. This minimum number is increased by the number of LVDS
pairs used in parallel operation. The MuxIt EVM uses two serializer-transmit-
ters and two LVDS pairs, which doubles the minimum number of data bits (four