Texas Instruments SN65HVD72EVM Evaluation Module SN65HVD72EVM SN65HVD72EVM Datenbogen
Produktcode
SN65HVD72EVM
Vcc
GND
B
A
D
R
1
2
4
5
6
7
8
DE
3
U1
RE
DUT_VCC
R5
120 W
0V
3.3V
Receive
Data
B
A
Transmit
Data
V
OD
0W
R8
0W
R9
B
A
V
A
V
B
Scope
Ch1
Ch2
Ch3
Ch4
PSU1
3.3V
Signal
Generator
JMP4
1
2
2
VCC
3
4
4
R
D
JMP3
1
2
2
VCC
3
4
4
JMP2
1
2
2
VCC
3
4
4
/RE
DE
JMP6
1
2
3
4
2
3
4
B
A
A
1
JMP11
2
3
3
1
JMP14
2
3
3
1
2
3
TB1
G
N
D
E
A
R
T
H
V
C
C
HVD7x
EVM
3.3V
Powering Up the EVM and Taking Measurements
Figure 4. Transceiver Configuration for Normal Operation
shows the corresponding EVM setup. EARTH and GND receive the same reference potential,
PSU-ground, through the wire-bridge from pin 1 to pin 2 at the terminal block, TB1, while pin 3 (VCC)
is connected to the 3.3-V output of a power-supply unit (PSU).
is connected to the 3.3-V output of a power-supply unit (PSU).
Figure 5. SN65HVD7xEVM Setup for Normal Transceiver Operation
The low potential for RE is provided by the wire-bridge from pin 2 to pin 3 at JMP2, and the high
potential for DE through a wire-bridge from pin 2 to pin 1 at JMP3. Data from the signal generator enter
the board at pin 2 and pin 3 of JMP4. This data is measured via channel 1, which is connected to pin 1
and pin 2 of JMP14. Channel 2 measures the receive data at JMP11, and channels 3 and 4 the bus
voltages, V
potential for DE through a wire-bridge from pin 2 to pin 1 at JMP3. Data from the signal generator enter
the board at pin 2 and pin 3 of JMP4. This data is measured via channel 1, which is connected to pin 1
and pin 2 of JMP14. Channel 2 measures the receive data at JMP11, and channels 3 and 4 the bus
voltages, V
A
and V
B
, at JMP6.
2. Operation Under Maximum Load
EIA-485 (RS-485) specifies three maximum load parameters: a maximum differential load of 60
Ω
, a
maximum common-mode load of 375
Ω
for each bus wire, and a receiver common-mode voltage
range from –7 V to +12 V.
reflects these requirements through R5, R8, R9, and V
CM
. Note that
under maximum load conditions the transceiver must be capable of sourcing and sinking bus currents
of up to 55 mA. The purpose of this test is to show the robustness of V
of up to 55 mA. The purpose of this test is to show the robustness of V
OD
over the entire common-
mode voltage range at maximum load.
5
SLLU162 – March 2012
SN65HVD7xEVM Evaluation Module
Copyright © 2012, Texas Instruments Incorporated