Texas Instruments DS100BR210EVK Evaluation Module DS100BR210EVK/NOPB DS100BR210EVK/NOPB Datenbogen
Produktcode
DS100BR210EVK/NOPB
INA+
INA-
OUTB+
VD
D
_
SEL
VI
N
1
8
INB+
INB-
1
7
1
4
1
3
1
6
L
O
S
VO
D
_
SEL
/
R
EAD
EN#
MO
D
E /
D
O
N
E
#
SD_
T
H
OUTA+
OUTA-
OUTB-
SMBUS AND
CONTROL
1
5
VDD
24
23
22
21
20
19
11
12
8
10
9
7
EQ
B
1
/AD
2
EN
SMB
1
2
5
6
3
SC
L
/D
EMB
EQ
B
0
/AD
3
SD
A
/D
EMA
4
VDD
T
X
_
D
IS
AD1/EQA1
AD0/EQA0
SNLS338E – JANUARY 2011 – REVISED FEBRUARY 2013
Pin Diagram
(1)
The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through
multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.
multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.
Figure 1. DS100BR111 Pin Diagram 24 lead
Copyright © 2011–2013, Texas Instruments Incorporated
3
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