Texas Instruments SRC4392EVM-PDK Evaluation Module SRC4392EVM-PDK SRC4392EVM-PDK Datenbogen
Produktcode
SRC4392EVM-PDK
NOTE: See Figure 82 for power-supply connections. Da
ptional connect on
o
e host.
shed lines denote o
i
t
s t
h
37
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48
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48
1
2
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5
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8
9
2
3
4
5
6
7
8
9
10
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12
11
12
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13
23
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21
20
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13
BCKA
LR KA
LR KA
C
SDI A
N
SDOUTA
NC
VIO
DGND3
BGND
SDOUTB
SDI B
NC
VIO
DGND3
BGND
SDOUTB
SDI B
N
LR KB
C
BCKB
RX +
1
RX -
1
RX +
2
RX -
2
RX +
3
RX -
3
RX +
4
RX -
4
VCC
AGND
AGND
LOCK
RX KO
C
SYNC
BLS
AESO T
U
VDD 3
3
TX+
TX-
DGND2
GP 4
O
GP 3
O
GP 2
O
GP 1
O
MCLK
RST
INT
SDA
A1
SCL
A0
CPM
VDD 8
1
DGND1
RDY
MUTE
RX KI
C
SRC4392IPFB
From Digital Inputs
(Line, Optica , Log
l
ic)
To Digital Outputs
(Line, Optical, Logic)
(Line, Optical, Logic)
To Host or Exte nal
r
Logic
To Host or Exte nal
r
Logic
I C
2
Ho t
s
Controller
Audio
I/O
Device
Audio
I/O
Device
DIR
Ref Clock
Master
Clock
DIR Recovered Clock
VIO
10kW
2.7kW
Tie
LO or HI
NOTE: See Figure 82 for power-supply connections. Da
ptional connections to the host.
shed lines denote o
37
38
39
40
41
42
43
44
45
46
47
48
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
10
11
12
11
12
36
35
34
33
32
31
30
29
28
27
26
25
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
23
22
21
20
19
18
17
16
15
14
13
BCKA
LRCKA
SDINA
SDOUTA
NC
VIO
DGND3
BGND
SDOUTB
SDINB
LRCKB
BCKB
LRCKA
SDINA
SDOUTA
NC
VIO
DGND3
BGND
SDOUTB
SDINB
LRCKB
BCKB
RX1+
RX1-
RX2+
RX2-
RX3+
RX3-
RX4+
RX4-
VCC
AGND
RX1-
RX2+
RX2-
RX3+
RX3-
RX4+
RX4-
VCC
AGND
LOCK
RXCKO
SYNC
BLS
AESOUT
VDD33
TX+
TX-
DGND2
GPO4
GPO3
GPO2
GPO1
MCLK
GPO3
GPO2
GPO1
MCLK
RST
INT
CDOUT
CDIN
CCLK
CS
CPM
VDD18
DGND1
RDY
MUTE
RXCKI
SRC4392IPFB
From Digita Inpu
l
ts
(Line, Optical, Logic)
To Digital Outputs
(L ne,
(L ne,
i
O
ca L
pti
l, ogic)
To Host o Exter al
r
n
Logic
To Host or xternal
E
Logic
SPI
Host
Controller
Audio
I/O
Device
Audio
I/O
Device
DIR
Ref Clock
Master
Clock
DIR Recovered Clock
VIO
10kW
SBFS029D – DECEMBER 2005 – REVISED DECEMBER 2012
Figure 80. Typical Application Diagram Using SPI Host Interface
Figure 81. Typical Application Diagram Using I
2
C Host Interface
Copyright © 2005–2012, Texas Instruments Incorporated
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