Texas Instruments TPS54560 Step-Down DC-DC Converter Evaluation Module TPS54560EVM-515 TPS54560EVM-515 Datenbogen
Produktcode
TPS54560EVM-515
(
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RIPPLE
OUT
L peak
I
1.591 A
I
I
5 A
5.797 A
2
2
=
+
=
+
=
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(
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(
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(
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( )
(
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2
2
OUT
OUT
IN max
2
2
OUT
L rms
O
SW
IN max
V
V
V
5 V
60 V - 5 V
1
1
I
I
5 A
5 A
12
V
L
12
60 V
7.2
H
400 kHz
æ
ö
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æ
ö
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ç
÷
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÷
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÷
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÷
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´
m
´
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ø
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÷
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ø
f
(
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(
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OUT
OUT
IN max
RIPPLE
O
SW
IN max
V
(V
V
)
5 V x (60 V - 5 V)
I
1.591 A
V
L
60 V x 7.2 H x 400 kHz
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-
=
=
=
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´
m
f
(
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(
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(
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OUT
IN max
OUT
O min
OUT
IND
SW
IN max
V
V
V
60 V - 5 V
5 V
L
7.6
H
I
K
V
5 A x 0.3
60 V
400 kHz
-
=
´
=
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=
m
´
´
´
f
SLVSBN0A – MARCH 2013 – REVISED MARCH 2014
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9.2.2.3 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.
supply the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.
shows the minimum output capacitance necessary, where
ΔI
OUT
is the change in output current, ƒsw
is the regulators switching frequency and
ΔV
OUT
is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in V
OUT
for a load step from 1.25 A to 3.75 A. Therefore,
ΔI
OUT
is 3.75 A - 1.25 A = 2.5 A and
ΔV
OUT
= 0.04 × 5 = 0.2 V. Using these numbers gives a minimum
capacitance of 62.5
μF. This value does not take the ESR of the output capacitor into account in the output
voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic
and tantalum capacitors have higher ESR that must be included in load step calculations.
and tantalum capacitors have higher ESR that must be included in load step calculations.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is
shown in . The excess energy absorbed in the output capacitor will increase the voltage on the capacitor. The
capacitor must be sized to maintain the desired output voltage during these transient periods.
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is
shown in . The excess energy absorbed in the output capacitor will increase the voltage on the capacitor. The
capacitor must be sized to maintain the desired output voltage during these transient periods.
calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where L
O
is the value of the inductor, I
OH
is the output current under heavy load, I
OL
is the output under light load, V
f
is the
peak output voltage, and Vi is the initial voltage. For this example, the worst case load step will be from 3.75 A to
1.25 A. The output voltage increases during this load transition and the stated maximum in our specification is
4 % of the output voltage. This makes V
1.25 A. The output voltage increases during this load transition and the stated maximum in our specification is
4 % of the output voltage. This makes V
f
= 1.04 × 5 = 5.2. Vi is the initial capacitor voltage which is the nominal
output
voltage
of
5
V.
Using
these
numbers
in
yields
a
minimum
capacitance
of
44.1
μF.
calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, V
ORIPPLE
is the maximum allowable output voltage ripple, and I
RIPPLE
is the
inductor ripple current.
yields 19.9
μF.
calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification.
indicates the ESR should be less than 15.7 m
Ω.
The most stringent criteria for the output capacitor is 62.5
μF required to maintain the output voltage within
regulation tolerance during a load transient.
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