Texas Instruments TLV70728EVM-612 Evaluation Module for 200 mA, Low IQ, Low-Dropout Regulator TLV70728EVM-612 TLV70728EVM-612 Datenbogen
Produktcode
TLV70728EVM-612
Thermal Guidelines and Layout Recommendations
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Thermal Guidelines and Layout Recommendations
Thermal management is a key component of design of any power converter and is especially important
when the power dissipation in the LDO is high. Use the following formula to approximate the maximum
power dissipation for the particular ambient temperature:
when the power dissipation in the LDO is high. Use the following formula to approximate the maximum
power dissipation for the particular ambient temperature:
T_j = T_a + Pd ×
q
_ja
where T_j is the junction temperature, T_a is the ambient temperature, P_d is the power dissipation in the
device (Watts), and
device (Watts), and
q
_ja is the thermal resistance from junction to ambient. All temperatures are in
degrees Celcius. The maximum silicon junction temperature, T_j, must not be allowed to exceed 150°C.
The layout design must use copper trace and plane areas effectively as thermal sinks, in order not to
allow T_j to exceed the absolute maximum rating under all temperature conditions and voltage conditions
across the part.
The layout design must use copper trace and plane areas effectively as thermal sinks, in order not to
allow T_j to exceed the absolute maximum rating under all temperature conditions and voltage conditions
across the part.
The designer must consider the layout carefully so that the thermal design of the PCB achieves optimal
performance over temperature. For this EVM,
performance over temperature. For this EVM,
shows that the DQN package footprint uses a
thermal pad to further cool the part. The thermal pad contains a single, 6-mil thermal via connection to the
bottom-side copper ground plane as well as a direct connection to the top-side surface copper over the
ground pad/pin for the IC. The PCB is a two-layer board with 2 ounces of copper on top and bottom
layers. The DQN package drawing can be found at the Texas Instruments Web site in the product folder
for the TPS707 LDO.
bottom-side copper ground plane as well as a direct connection to the top-side surface copper over the
ground pad/pin for the IC. The PCB is a two-layer board with 2 ounces of copper on top and bottom
layers. The DQN package drawing can be found at the Texas Instruments Web site in the product folder
for the TPS707 LDO.
repeats information from the Dissipation Ratings Table of the TPS707 (
) data sheet for
comparison with the thermal resistance,
q
_ja, calculated for this EVM layout to show the wide variation in
thermal resistances for given copper areas. The high-K value is determined using a standard JEDEC
high-k (2s2p) board having dimensions of 3 inch × 3 inch with 1-ounce internal power and ground planes
and 2-ounce copper traces on top and bottom of the board.
high-k (2s2p) board having dimensions of 3 inch × 3 inch with 1-ounce internal power and ground planes
and 2-ounce copper traces on top and bottom of the board.
Table 1. EVM Thermal Resistance,
q
_ja , and Maximum Power Dissipation
Max. Dissipation Without Derating
Max. Dissipation Without Derating
Board
Package
q
_ja
(T
A
= 25°C)
(T
A
= 70°C)
High-K
DQN
206°C/W
485 mW
269 mW
TPS70728EVM-612
DQN
88°C/W
1.136 W
625 mW
The thermal resistance for the TPS70728EVM-612,
q
_ja, is the measured value for this particular layout
scheme. The maximum power dissipation is proportional to the volume of copper volume connected to the
package.
package.
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Board Layout
Figure 3. Assembly Layer
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TPS70728EVM-612
SLVU416 – December 2010
© 2010, Texas Instruments Incorporated