Texas Instruments DS90UR916Q Evaluation Module SERDESUR-916ROS/NOPB SERDESUR-916ROS/NOPB Datenbogen
Produktcode
SERDESUR-916ROS/NOPB
RIN-
DS90UR916Q
±
DESERIALIZER
RIN+
Clock and
Data
Recovery
Timing and
Control
24
LOCK
PCLK
SSCG
O
u
tp
u
t
L
a
tch
Se
ri
a
l
to
Pa
ra
lle
l
D
C
Ba
la
n
ce
D
e
co
d
e
r
PASS
RGB [7:0]
HS
VS
DE
Error
Detector
PDB
BISTEN
CMF
SCL
SCA
ID[x]
ID[x]
STRAP INPUT
CONFIG [1:0]
LF_MODE
OS_PCLK/DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
MAPSEL [1:0]
LF_MODE
OS_PCLK/DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
MAPSEL [1:0]
STRAP INPUT
OP_LOW
F
R
C
D
it
h
e
ri
n
g
1
W
h
it
e
Ba
la
n
ce
L
U
T
F
R
C
D
it
h
e
ri
n
g
2
R[7:0]
HS
VS
VS
PCLK
PDB
Serializer
Deserializer
DE
R
G
B
D
ig
it
a
l
D
isp
la
y
In
te
rf
a
ce
HOST
Graphics
Processor
FPD-Link II
1 Pair / AC Coupled
DS90UR905Q
DS90UR916Q
100 ohm STP Cable
PASS
V
DDIO
PDB
SCL
SDA
CONFIG [1:0]
RFB
RFB
VODSEL
DeEmph
DeEmph
BISTEN
BISTEN
LOCK
ID[x]
DAP
DAP
CMF
100 nF
100 nF
G[7:0]
B[7:0]
SCL
SDA
ID[x]
R[7:0]
HS
VS
VS
PCLK
DE
G[7:0]
B[7:0]
STRAP pins
not shown
RIN+
RIN-
DOUT+
DOUT-
Optional
Optional
(1.8V or 3.3V)
(1.8V or 3.3V) 1.8V
1.8V
V
DDIO
V
DDn
V
DDn
RGB Display
QVGA to XGA
24-bit or
18-bit dithered
color depth
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
Applications Diagram
Figure 1.
Block Diagrams
Figure 2.
2
Copyright © 2011–2013, Texas Instruments Incorporated
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