Texas Instruments IC MCU 16B MSP430F2419TPM LQFP-64 TID MSP430F2419TPM Datenbogen
Produktcode
MSP430F2419TPM
MSP430F261x
MSP430F241x
MSP430F241x
SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012
Outputs (Ports P1 Through P8)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
I
(OHmax)
= -1.5 mA
(1)
2.2 V
V
CC
- 0.25
V
CC
I
(OHmax)
= -6 mA
(2)
2.2 V
V
CC
- 0.6
V
CC
V
OH
High-level output voltage
V
I
(OHmax)
= -1.5 mA
(1)
3 V
V
CC
- 0.25
V
CC
I
(OHmax)
= -6 mA
(2)
3 V
V
CC
- 0.6
V
CC
I
(OLmax)
= 1.5 mA
(1)
2.2 V
V
SS
V
SS
+ 0.25
I
(OLmax)
= 6 mA
(2)
2.2 V
V
SS
V
SS
+ 0.6
V
OL
Low-level output voltage
V
I
(OLmax)
= 1.5 mA
(1)
3 V
V
SS
V
SS
+ 0.25
I
(OLmax)
= 6 mA
(2)
3 V
V
SS
V
SS
+ 0.6
(1)
The maximum total current, I
(OHmax)
and I
(OLmax)
, for all outputs combined should not exceed ±12 mA to hold the maximum voltage drop
specified.
(2)
The maximum total current, I
(OHmax)
and I
(OLmax)
, for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Ports P1 Through P8)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
2.2 V
dc
10
Port output frequency
f
Px.y
P1.4/SMCLK, C
L
= 20 pF, R
L
= 1 k
Ω
(1) (2)
MHz
(with load)
3 V
dc
12
2.2 V
dc
12
f
Port°CLK
Clock output frequency
P2.0/ACLK/CA2, P1.4/SMCLK, C
L
= 20 pF
(2)
MHz
3 V
dc
16
P5.6/ACLK, C
L
= 20 pF, LF mode
30
50
70
P5.6/ACLK, C
L
= 20 pF, XT1 mode
40
50
60
P5.4/MCLK, C
L
= 20 pF, XT1 mode
40
60
Duty cycle of output
50% -
50% +
t
(Xdc)
%
P5.4/MCLK, C
L
= 20 pF, DCO
frequency
15 ns
15 ns
P1.4/SMCLK, C
L
= 20 pF, XT2 mode
40
60
50% -
50% +
P1.4/SMCLK, C
L
= 20 pF, DCO
15 ns
15 ns
(1)
A resistive divider with two 0.5-k
Ω
resistors between V
CC
and V
SS
is used as load. The output is connected to the center tap of the
divider.
(2)
The output voltage reaches at least 10% and 90% V
CC
at the specified toggle frequency.
36
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