Texas Instruments Evaluation Module for Integrated 3.3V / 5V Power LDO with Clock Output TPS51103EVM TPS51103EVM Datenbogen
Produktcode
TPS51103EVM
5
Typical Characteristics
5.1
Load Regulation
0
6 V
12 V
20 V
V
IN
(V)
20
40
60
80
100
4.84
4.86
4.92
4.88
4.90
4.94
4.96
4.98
5.00
6 V
20 V
12 V
V
V
R
E
G
5
–
O
u
tp
u
t
V
o
lt
a
g
e
–
V
I
OUT
– Output Current – mA
VREG5 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
0
6 V
12 V
20 V
V
IN
(V)
20
40
60
80
100
3.22
3.23
3.27
3.24
3.25
3.28
3.29
3.30
3.31
6 V
20 V
12 V
I
OUT
– Output Current – mA
3.26
VREG3 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
V
V
R
E
G
3
–
O
u
tp
u
t
V
o
lt
a
g
e
–
V
0
2
4
6
8
10
0
2
8
4
6
10
12
14
16
V
1
5
_
V
O
U
T
–
O
u
tp
u
t
V
o
lt
a
g
e
–
V
I
OUT
– Output Current – mA
15V_OUT OUTPUT VOLTAGE
vs
OUTPUT CURRENT
0
6 V
12 V
20 V
V
IN
(V)
1
2
3
4
5
3.22
3.23
3.27
3.24
3.25
3.28
3.29
3.30
3.31
6 V
20 V
12 V
V
V
R
T
C
3
–
O
u
tp
u
t
V
o
lt
a
g
e
–
V
I
OUT
– Output Current – mA
3.26
VRTC3 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
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Typical Characteristics
through
present typical performance graphs for the TPS51103EVM. Because actual
performance data can be affected by measurement techniques and environmental variables, these curves
are presented for reference only and may differ from actual field measurements.
are presented for reference only and may differ from actual field measurements.
Figure 5. VREG5 Load Regulation
Figure 6. VREG3 Load Regulation
Figure 7. 15V_OUT Load Regulation
Figure 8. VRTC3 Load Regulation
SLUU303A – JUNE 2008 – Revised SEPTEMBER 2008 Using the TPS51103EVM Integrated 3.3-V/5-V Power LDO with Clock Output
9