Texas Instruments DS100KR800EVK evaluation board DS100KR800EVK/NOPB DS100KR800EVK/NOPB Datenbogen
Produktcode
DS100KR800EVK/NOPB
46
47
48
49
50
51
52
53
54
43
42
41
40
39
38
37
36
22
27
26
25
24
23
21
20
19
45
44
3
4
5
6
7
8
9
10
1
2
GND
BOTTOM OF PKG
13
14
15
16
17
18
11
12
33
32
31
30
29
28
35
34
VDD
VDD
VDD
VDD
100 mils
20 mils
20 mils
VDD
INTERNAL STRIPLINE
EXTERNAL MICROSTRIP
SNLS340D – NOVEMBER 2011 – REVISED APRIL 2013
APPLICATIONS INFORMATION
GENERAL RECOMMENDATIONS
The DS100KR800 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the information below and Revision 4 of the LVDS Owner's Manual for more detailed information on high
speed design tips to address signal integrity design issues.
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the information below and Revision 4 of the LVDS Owner's Manual for more detailed information on high
speed design tips to address signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and outputs have been optimized to work with interconnects using a controlled differential
impedance of 85 - 100
impedance of 85 - 100
Ω
. It is preferable to route differential lines exclusively on one layer of the board,
particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-
1187 (
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-
1187 (
) for additional information on WQFN packages.
Figure 6. Typical Routing Options
shown above depicts different transmission line topologies which can be used in various combinations
to achieve the optimal system performance. Impedance discontinuities at the differential via can be minimized or
eliminated by increasing the swell around each hole and providing for a low inductance return current path. When
the via structure is associated with thick backplane PCB, further optimization such as back drilling is often used
to reduce the detrimental high frequency effects of stubs on the signal path.
eliminated by increasing the swell around each hole and providing for a low inductance return current path. When
the via structure is associated with thick backplane PCB, further optimization such as back drilling is often used
to reduce the detrimental high frequency effects of stubs on the signal path.
28
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: