Texas Instruments PCM5122 Evaluation Module PCM5122EVM-U PCM5122EVM-U Datenbogen
Produktcode
PCM5122EVM-U
PLLCKIN x R x J.D
PLLCK =
P
PLLCKIN x R x K
or PLLCK =
P
SLAS759A – AUGUST 2012 – REVISED SEPTEMBER 2012
PLL Calculation
The PCM514x has an on-chip PLL with fractional multiplication to generate the clock frequency needed by the
audio DAC, Negative Charge Pump, Modulator and Digital Signal Processing blocks. The programmability of the
PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN)
supports clock frequencies from 512kHz to 50MHz and is register programmable to enable generation of
required sampling rates with fine precision.
audio DAC, Negative Charge Pump, Modulator and Digital Signal Processing blocks. The programmability of the
PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN)
supports clock frequencies from 512kHz to 50MHz and is register programmable to enable generation of
required sampling rates with fine precision.
The PLL is enabled by default. The PLL can be turned on by writing to Page 0, Register 4, D(0). When the PLL
is enabled, the PLL output clock PLLCK is given by
is enabled, the PLL output clock PLLCK is given by
:
(1)
R = 1, 2, 3,4, ... , 15, 16
J = 4,5,6, . . . 63, and D = 0000, 0001, 0002, . . . 9999
K = [J value].[D value]
P = 1, 2, 3, ... 15
R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while
D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).
D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).
Examples:
•
•
If K = 8.5, then J = 8, D = 5000
•
If K = 7.12, then J = 7, D = 1200
•
If K = 14.03, then J = 14, D = 0300
•
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied:
•
•
1MHz
≤
( PLLCKIN / P )
≤
20MHz
•
64MHz
≤
(PLLCKIN x K x R / P )
≤
100MHz (in VREF mode)
•
72MHz
≤
(PLLCKIN x K x R / P )
≤
86MHz (in VCOM mode)
•
1
≤
J
≤
63
When the PLL is enabled and D
≠
0000, the following conditions must be satisfied:
•
6.667MHz
≤
PLLCLKIN / P
≤
20MHz
•
64MHz
≤
(PLLCKIN x K x R / P )
≤
100MHz (in VREF mode)
•
72MHz
≤
(PLLCK IN x K x R / P )
≤
86MHz (in VCOM mode)
•
4
≤
J
≤
11
•
R = 1
When the PLL is enabled,
•
•
f
S
= (PLLCLKIN × K × R) / (2048 × P)
•
The value of N is selected so that f
S
× N = PLLCLKIN x K x R / P is in the allowable range.
Example: MCLK = 12MHz and f
S
= 44.1kHz, (N=2048)
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example: MCLK = 12MHz and f
S
= 48.0kHz, (N=2048)
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
Values are written to the registers in
Copyright © 2012, Texas Instruments Incorporated
25
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