Texas Instruments PCM5142 Evaluation Module PCM5142EVM-U PCM5142EVM-U Datenbogen
Produktcode
PCM5142EVM-U
C
P
V
D
D
C
A
P
P
C
P
G
N
D
C
A
P
M
V
N
E
G
O
U
T
L
O
U
T
R
A
V
D
D
A
G
N
D
V
C
O
M
M
O
S
I
M
C
G
P
IO
5
G
P
IO
4
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
D
V
D
D
D
G
N
D
L
D
O
O
X
S
M
T
M
IS
O
L
R
C
K
D
IN
B
C
K
S
C
K
G
P
IO
6
M
S
M
O
D
E
1
G
P
IO
2
G
P
IO
3
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
SLAS759A – AUGUST 2012 – REVISED SEPTEMBER 2012
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DEVICE INFORMATION
PCM514x pin assignments-1 MODE1 tied DVDD : SPI mode
PCM514x (top view)
Table 2. PCM514x SPI mode Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
PIN
CPVDD
1
-
Charge pump power supply, 3.3V
CAPP
2
O
Charge pump flying capacitor terminal for positive rail
CPGND
3
-
Charge pump ground
CAPM
4
O
Charge pump flying capacitor terminal for negative rail
VNEG
5
O
Negative charge pump rail terminal for decoupling, -3.3V
OUTL
6
O
Analog output from DAC left channel
OUTR
7
O
Analog output from DAC right channel
AVDD
8
-
Analog power supply, 3.3V
AGND
9
-
Analog ground
VCOM output (Optional mode selected by register; default setting is VREF mode.) When in
VCOM
10
O
VREF mode (default), this pin ties to GND. When in VCOM mode, decoupling capacitor to
GND is required.
GND is required.
MOSI
11
I
Input data for SPI
(1)
MC
12
I
Input clock for SPI
(1)
GPIO5
13
I/O
General purpose digital input and output port
GPIO4
14
I/O
General purpose digital input and output port
GPIO3
15
I/O
General purpose digital input and output port
GPIO2
16
I/O
General purpose digital input and output port
MODE1
17
I
Mode control selection pin
(1)
•
MODE1=Low, MODE2=Low : Hardwired mode
•
MODE1=Low, MODE2=High : I
2
C mode
MS (MODE2)
18
I
•
MODE1=High : SPI mode, MODE2 pin changes MS pin (chip select for
SPI)
SPI)
GPIO6
19
I/O
General purpose digital input and output port
SCK
20
I
System clock input
(1)
BCK
21
I/O
Audio data bit clock input (slave) or output (master)
(1)
DIN
22
I
Audio data input
(1)
LRCK
23
I/O
Audio data word clock input (slave) or output (master)
(1)
Primary output data for SPI readback
MISO (GPIO1)
24
I/O
Secondary; general purpose digital input/output port controlled by register
XSMT
25
I
Soft mute control
(1)
Soft mute (Low) / soft un-mute (High)
(1)
Failsafe LVCMOS Schmitt trigger input.
Copyright © 2012, Texas Instruments Incorporated
3
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