Texas Instruments TPA3110D2 Evaluation Module TPA3110D2EVM TPA3110D2EVM Datenbogen
Produktcode
TPA3110D2EVM
Operation
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Power Supply
A single power supply is required to power up the EVM. Since most of the pins are PVCC compliant, the
PVCC supply can also be used to power the analog supply (AV
PVCC supply can also be used to power the analog supply (AV
CC
) and can be used to pull up the logic
pins for shutdown (SD) control, fault detection (FAULT), gain (GAIN0 and GAIN1), and PBTL as long as
the voltage slew rate is limited to 10 V/ms. GVDD is an internally generated supply for the output FETs
and is also used to power the PLIMIT voltage divider circuit on the EVM. PLIMIT is GVDD compliant, but
not PVCC compliant. PLIMIT can also be powered by an external supply connected to the PLIMIT pin.
Take care not to power the PLIMIT pin (or connect power to the GVDD pin inadvertently through the
PLIMIT network) when the PVCC supply is turned off. This can cause damage to the IC.
the voltage slew rate is limited to 10 V/ms. GVDD is an internally generated supply for the output FETs
and is also used to power the PLIMIT voltage divider circuit on the EVM. PLIMIT is GVDD compliant, but
not PVCC compliant. PLIMIT can also be powered by an external supply connected to the PLIMIT pin.
Take care not to power the PLIMIT pin (or connect power to the GVDD pin inadvertently through the
PLIMIT network) when the PVCC supply is turned off. This can cause damage to the IC.
Table 2. Power Supply Requirements
Description
Voltage Range
Current Requirements
Minimum Wire Size
PVCC
8 to 26 V
3 A
24 AWG
Evaluation Module Preparations
1. Ensure that the external power source is set to OFF.
2. Connect the external regulated power supply adjusted from 8V to 26V to the module PVCC and GND
2. Connect the external regulated power supply adjusted from 8V to 26V to the module PVCC and GND
banana jacks taking care to observe marked polarity.
Inputs and Outputs
1. For a BTL Configuration, connect a Load(s) across the outputs (LEFT+ and LEFT-) and (RIGHT+ and
RIGHT-). For PBTL configuration, connect a single load from one of the left speaker jacks to one of the
right speaker jacks depending on how the filters are loaded.
right speaker jacks depending on how the filters are loaded.
2. Connect audio inputs, either differential or single-ended, to the LIN and RIN RCA phono plugs for BTL
operation. For PBTL operation, apply a single input, differential or single-ended, to the RIN RCA phono
plug.
plug.
Control Inputs
1. Ensure the mode jumpers, PBTL, GAIN0, GAIN1, are set correctly depending on the desired operating
state. Also, make sure to connect the left outputs together and the right outputs together at the LEFT
and RIGHT molex connectors if PBTL operation is desired.
and RIGHT molex connectors if PBTL operation is desired.
Power Up
1. Verify correct voltage and input polarity and turn the external power supplies ON
The EVM should begin operation.
2. Adjust the audio source for the correct volume and enjoy!
Table 3. TPA3110D2 Control Guide
Control
Function
Options
Notes
JP1
Allow amp to self reset after
Insert jumper for self reset.
For latched SC fault, cycle power to reset the fault
short-circuit protection event
Leave off for latched SC fault latch.
GAIN1/GAIN0
Controls amp gain
Insert jumper for zero state
00 = 20 dB (GAIN1, GAIN0)
(low), Leave off for one state
01 = 26 dB
(high)
10 = 32 dB
11 = 36 dB
11 = 36 dB
JP2
Defeats PLIMIT function and allows
Insert jumper for PLIMIT
JP2 connects PLIMIT directly to GVDD
amp to run at full power.
defeat
R7
Adjust PLIMIT (an external voltage can
The output voltage rails will be limited to
also be applied to the PLIMIT test
approximately 4X the voltage at the PLIMIT pin.
point)
Take care not to apply power to PLIMIT when the
PVCC source is off.
PVCC source is off.
4
TPA3110D2 EVM Audio Amplifier Evaluation Board
SLOU263A – July 2009 – Revised July 2010
Copyright © 2009–2010, Texas Instruments Incorporated