Texas Instruments TAS5705 Evaluation Module TAS5705EVM2 TAS5705EVM2 Datenbogen

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TAS5705EVM2

Appendix A 2 X BTL BD (Default: BD mode)

Appendix A

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Following initial scripts may also be found on the installation CD or TI Web site. The following scripts
use .ini format where the first column is type of write command ("01" means single byte, "02"
means multi-byte, "00" means comment), the following column is the I2C address and then
followed by data(s).

Oscillator Trim

System Control Register 1

Serial Data Interface Register

Soft Mute Register

Master Volume Register (0xFF = Mute)

Channel 1 Volume

Channel 2 Volume

Channel 3 Volume

Channel 4 Volume

Channel 5 Volume

Channel 6 Volume

Micro Register

Modulation Limit

Shutdown Group Resister

Split Capacitor Charge Period

Back-end Error Register

(Below) Input Mux Register

(Below) Downmix Register

(Below) AM Mode Register

(Below) Biquad1 Coeff

(Below) Biquad2 Coeff

(Below) PWM Output MUX Register (Note: Writes to this register affect Inter-Channel Delay)

(Below) 1/G

(Below) Scale = 1/(1-1/G)

Inter-Channel Delay Channel 1

Inter-Channel Delay Channel 2

Inter-Channel Delay Channel 3

Inter-Channel Delay Channel 4

Inter-Channel Delay Channel 5

Inter-Channel Delay Channel 6

Offset Register (Absolute Delay)

System Control Register 2 (active)

2 X BTL BD (Default: BD mode)

SLOU223A – December 2008 – Revised January 2009

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