Microchip Technology MA330018 Datenbogen

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04

DS70291G-page 150

REGISTER 9-3:

PLLFBD: PLL FEEDBACK DIVISOR REGISTER

(1)

U-0

R/W-0

(1)

—

PLLDIV<8>

bit 15

bit 8

R/W-0

R/W-1

R/W-0

PLLDIV<7:0>

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-9

Unimplemented: Read as ‘0’

bit 8-0

PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
111111111 = 513
•
•
•
000110000 = 50 (default)
•
•
•
000000010 = 4
000000001 = 3
000000000 = 2

Note 1: This register is reset only on a Power-on Reset (POR).