Microchip Technology MA330017 Datenbogen
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
DS70283K-page 10
© 2007-2012 Microchip Technology Inc.
FIGURE 1-1:
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 BLOCK DIAGRAM
16
OSC1/CLKI
OSC2/CLKO
V
DD
, V
SS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Voltage
V
CAP
IC1,2,7,8
I2C1
PORTA
Note:
Not all pins or features are implemented on all device pinout configurations. See
for the specific pins
and features present on each device.
Instruction
Decode and
Control
PCH PCL
16
Program Counter
16-bit ALU
23
23
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
16
EA MUX
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Address Latch
Program Memory
Data Latch
Literal Dat
a
16
16
16
16
Data Latch
Address
Latch
16
X RAM
Y RAM
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
Control Signals
to Various Blocks
ADC1
Timers
PORTB
Address Generator Units
1-3
CNx
UART1
OC/
PWM1-2
QEI
PWM
2 Ch
PWM
6 Ch
Remappable
Pins
16
PORTC
SPI1