Microchip Technology MA330031-2 Datenbogen
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 208
2011-2013 Microchip Technology Inc.
FIGURE 13-1:
TYPE B TIMER BLOCK DIAGRAM (x = 2 AND 4)
FIGURE 13-2:
TYPE C TIMER BLOCK DIAGRAM (x = 3 AND 5)
Note
1:
F
P
is the peripheral clock.
TGATE
TCS
00
10
x1
PRx
TGATE
Set TxIF Flag
0
1
Equal
Reset
TxCK
TCKPS<1:0>
Gate
Sync
Sync
F
P(1)
Falling Edge
Detect
TCKPS<1:0>
Latch
Data
CLK
TxCLK
TMRx
Comparator
Prescaler
(/n)
Prescaler
(/n)
Sync
Note
1:
F
P
is the peripheral clock.
2:
The ADC trigger is available on TMR3 and TMR5 only.
TGATE
TCS
00
10
x1
PRx
TGATE
Set TxIF Flag
0
1
Equal
Reset
TxCK
TCKPS<1:0>
Gate
Sync
Sync
F
P(1)
Falling Edge
Detect
TCKPS<1:0>
Latch
Data
CLK
TxCLK
TMRx
Comparator
Prescaler
(/n)
Prescaler
(/n)
Sync
ADC Start of
Conversion Trigger
(2)