Microchip Technology MCP3421DM-WS Datenbogen
© 2009 Microchip Technology Inc.
DS39632E-page 51
PIC18F2455/2550/4455/4550
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO V
DD
, V
DD
RISE > T
PWRT
)
FIGURE 4-7:
TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO V
DD
)
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V
1V
5V
T
PWRT
T
OST
T
PWRT
T
OST
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
T
PLL
Note:
T
OST
= 1024 clock cycles.
T
PLL
≈ 2 ms max. First three stages of the Power-up Timer.