Microchip Technology DM164134 Datenbogen
PIC18FXX8
DS41159E-page 76
© 2006 Microchip Technology Inc.
Example 7-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 7-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
unsigned multiply. Equation 7-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 7-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
MULTIPLICATION
ALGORITHM
EXAMPLE 7-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MULTIPLY ROUTINE
Example 7-4 shows the sequence to do a 16 x 16
signed multiply. Equation 7-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pair’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
signed multiply. Equation 7-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pair’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
EQUATION 7-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
MULTIPLICATION
ALGORITHM
EXAMPLE 7-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MULTIPLY ROUTINE
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF
PRODH, RES1
;
MOVFF
PRODL, RES0
;
;
MOVF
ARG1H, W
MULWF
ARG2H
; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF
PRODH, RES3
;
MOVFF
PRODL, RES2
;
;
MOVF
ARG1L, W
MULWF
ARG2H
; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1
; Add cross
MOVF
PRODH, W
; products
ADDWFC
RES2
;
CLRF
WREG
;
ADDWFC
RES3
;
;
MOVF
ARG1H, W
;
MULWF
ARG2L
; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1
; Add cross
MOVF
PRODH, W
; products
ADDWFC
RES2
;
CLRF
WREG
;
ADDWFC
RES3
;
RES3:RES0
=
ARG1H:ARG1L
• ARG2H:ARG2L
=
(ARG1H
• ARG2H • 2
16
) +
(ARG1H
• ARG2L • 2
8
) +
(ARG1L
• ARG2H • 2
8
) +
(ARG1L
• ARG2L)
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF
PRODH, RES1
;
MOVFF
PRODL, RES0
;
;
MOVF
ARG1H, W
MULWF
ARG2H
; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF
PRODH, RES3
;
MOVFF
PRODL, RES2
;
;
MOVF
ARG1L, W
MULWF
ARG2H
; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1
; Add cross
MOVF
PRODH, W
; products
ADDWFC
RES2
;
CLRF
WREG
;
ADDWFC
RES3
;
;
MOVF
ARG1H, W
;
MULWF
ARG2L
; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1
; Add cross
MOVF
PRODH, W
; products
ADDWFC RES2
;
CLRF
WREG
;
ADDWFC
RES3
;
;
BTFSS
ARG2H, 7
; ARG2H:ARG2L neg?
BRA
SIGN_ARG1
; no, check ARG1
MOVF
ARG1L, W
;
SUBWF
RES2
;
MOVF
ARG1H, W
;
SUBWFB
RES3
;
SIGN_ARG1
BTFSS
ARG1H, 7
; ARG1H:ARG1L neg?
BRA
CONT_CODE
; no, done
MOVF
ARG2L, W
;
SUBWF
RES2
;
MOVF
ARG2H, W
;
SUBWFB
RES3
;
CONT_CODE
:
RES3:RES0
=
ARG1H:ARG1L
• ARG2H:ARG2L
=
(ARG1H
• ARG2H • 2
16
) +
(ARG1H
• ARG2L • 2
8
) +
(ARG1L
• ARG2H • 2
8
) +
(ARG1L
• ARG2L)+
(-1
• ARG2H<7> • ARG1H:ARG1L • 2
16
) +
(-1
• ARG1H<7> • ARG2H:ARG2L • 2
16
)