Freescale Semiconductor Xtrinsic MAG3110 Magnetometer RD4247MAG3110 RD4247MAG3110 Datenbogen
Produktcode
RD4247MAG3110
MAG3110
Sensors
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
17
5.1.2
OUT_X_MSB (0x01), OUT_X_LSB (0x02), OUT_Y_MSB (0x03), OUT_Y_LSB (0x04),
OUT_Z_MSB (0x05), OUT_Z_LSB (0x06)
OUT_Z_MSB (0x05), OUT_Z_LSB (0x06)
X-axis, Y-axis, and Z-axis 16-bit output sample data of the magnetic field strength expressed as signed 2's complement numbers.
When RAW bit is set (CTRL_REG2[RAW] = 1), the output range is between -20,000 to 20,000 bit counts (the combination of the
1000
1000
T full scale range and the zero-flux offset ranging up to 1000 T).
When RAW bit is clear (CTRL_REG2[RAW] = 0), the output range is between -30,000 to 30,000 bit counts when the user offset
ranging between -10,000 to 10,000 bit counts are included.
ranging between -10,000 to 10,000 bit counts are included.
The DR_STATUS register, OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB are stored
in the auto-incrementing address range of 0x00 to 0x06. Data acquisition is a sequential read of 6 bytes.
in the auto-incrementing address range of 0x00 to 0x06. Data acquisition is a sequential read of 6 bytes.
If the Fast Read (FR) bit is set in CTRL_REG1 (0x10), auto-increment will skip over LSB of the X, Y, Z sample registers. This will
shorten the data acquisition from 6 bytes to 3 bytes. If the LSB registers are directly addressed, the LSB information can still be
read regardless of FR bit setting.
shorten the data acquisition from 6 bytes to 3 bytes. If the LSB registers are directly addressed, the LSB information can still be
read regardless of FR bit setting.
The preferred method for reading data registers is the burst-read method where the user application acquires data sequentially
starting from register 0x01. If register 0x01 is not read first, the rest of the data registers (0x02 - 0x06) will not be updated with
the most recent acquisition. It is still possible to address individual data registers, however register 0x01 must be read prior to
ensure that the latest acquisition data is being read.
starting from register 0x01. If register 0x01 is not read first, the rest of the data registers (0x02 - 0x06) will not be updated with
the most recent acquisition. It is still possible to address individual data registers, however register 0x01 must be read prior to
ensure that the latest acquisition data is being read.
Table 14. OUT_X_MSB Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XD15
XD14
XD13
XD12
XD11
XD10
XD9
XD8
Table 15. OUT_X_LSB Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XD7
XD6
XD5
XD4
XD3
XD2
XD1
XD0
Table 16. OUT_Y_MSB Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
YD15
YD14
YD13
YD12
YD11
YD10
YD9
YD8
Table 17. OUT_Y_LSB Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
YD7
YD6
YD5
YD4
YD3
YD2
YD1
YD0
Table 18. OUT_Z_MSB Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ZD15
ZD14
ZD13
ZD12
ZD11
ZD10
ZD9
ZD8
Table 19. OUT_Z_LSB Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ZD6
ZD6
ZD5
ZD4
ZD3
ZD2
ZD1
ZD0