Freescale Semiconductor Evaluation Board for MCF52223 M52223EVB M52223EVB Datenbogen

Freescale Semiconductor

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The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable counter driven by a 
seven-stage programmable prescaler. Each of the four channels can be configured for input capture or output compare. 
Additionally, channel three, can be configured as a pulse accumulator.

A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. 
The input capture and output compare functions allow simultaneous input waveform measurements and output waveform 
generation. The input capture function can capture the time of a selected transition edge. The output compare function can 
generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a 
gated time accumulator.

The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal 
processor intervention. Each timer can count down from the value written in its PIT modulus register or it can be a free-running 
down-counter. 

The Real-Time Clock (RTC) module maintains the system (time-of-day) clock and provides stopwatch, alarm, and interrupt 
functions. It includes full clock features: seconds, minutes, hours, days and supports a host of time-of-day interrupt functions 
along with an alarm interrupt.

The device has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a dedicated 
counter. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 
100%. The PWM outputs have programmable polarity, and can be programmed as left aligned outputs or center aligned outputs. 
For higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated 
to form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels.

The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running 
down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.

The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced 
frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL, 
crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are 
powered by the normal supply pins, VDD and VSS.

The device has a single interrupt controller that supports up to 63 interrupt sources. There are 56 programmable sources, 49 of 
which are assigned to unique peripheral interrupt requests. The remaining seven sources are unassigned and may be used for 
software interrupt requests.