Freescale Semiconductor Evaluation Kit for Qorivva MPC5534, eTPU connector, CAN, LIN MPC5553EVBE MPC5553EVBE Datenbogen

Freescale Semiconductor

10

The following table lists the V

RC

 and POR electrical specifications:

1

All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2

Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification requirements, 
which includes the complete DC parametric and functional testing at room temperature and hot temperature.

ESD for human body model (HBM)

2000

V

HBM circuit description

R1

1500



C

100

pF

ESD for field induced charge model (FDCM)

500 (all pins)

V

750 (corner pins)

Number of pulses per pin:

Positive pulses (HBM)
Negative pulses (HBM)

 

—
—

1
1

—
—

Interval of pulses

—

1

second

1

1.5  V  (V

DD

) POR 

1

Negated (ramp up)
Asserted (ramp down)

V

POR15

1.1
1.1

1.35
1.35

V

2

3.3  V  (V

DDSYN

Asserted (ramp up)
Negated (ramp up)
Asserted (ramp down)
Negated (ramp down)

V

POR33

0.0
2.0
2.0
0.0

0.30
2.85
2.85
0.30

V

3

RESET pin supply 
(V

DDEH6

1, 

2

Negated (ramp up)

Asserted (ramp down)

 

V

POR5

2.0
2.0

2.85
2.85

V

4

V

RC33

 voltage

Before V

RC

 allows the pass 

transistor to start turning on

V

TRANS_START

1.0

2.0

V

5

When V

RC

 allows the pass 

transistor to completely turn on 

3,

 

4

V

TRANS_ON

2.0

2.85

V

6

When the voltage is greater than 
the voltage at which the V

RC

 keeps 

the 1.5 V supply in regulation 

5, 6

V

VRC33REG

3.0

—

V

Current can be sourced

–40

o

 

C

11.0

—

mA

7

by V

RCCTL 

at Tj:

25

o

 

C

I

VRCCTL 

7

9.0

—

mA

150

o

 C

7.5

—

mA

8

Voltage differential during power up such that:
V

DD33

 can lag V

DDSYN

 or V

DDEH6

 before V

DDSYN

 and V

DDEH6

 reach the 

V

POR33

 and V

POR5

 minimums respectively.

V

DD33_LAG

—

1.0

V