Freescale Semiconductor Evaluation Board for MPC5500 Series MPC5554EVBE MPC5554EVBE Datenbogen

Freescale Semiconductor

11

Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase 
of the current consumed by V

RC33

. If V

RC33

 lags V

DDSYN

 by more than 100 mV, the increase in current 

consumed can drop V

DD

 low enough to assert the 1.5 V POR again. Oscillations are possible when the 

1.5 V POR asserts and stops the system clock, causing the voltage on V

DD

 to rise until the 1.5 V POR 

negates again. All oscillations stop when V

RC33

 is powered sufficiently.

When powering down, V

RC33

 and V

DDSYN

 have no delta requirement to each other, because the bypass 

capacitors internal and external to the device are already charged. When not powering up or down, no delta 
between V

RC33

 and V

DDSYN

 is required for the V

RC

 to operate within specification.

There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current 
spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending 
on which supplies are powered.

 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).

 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and 

pad_sh (slow type).

The values in 

 do not include the effect of the weak-pull devices on the output pins 

during power up. 

Before exiting the internal POR state, the voltage on the pins go to a high-impedance state until POR 
negates. When the internal POR negates, the functional state of the signal during reset applies and the 
weak-pull devices 
(up or down) are enabled as defined in the device reference manual. If V

DD

 is too low to correctly 

propagate the logic signals, the weak-pull devices can pull the signals to V

DDE

 and V

DDEH

.

Low

—

—

Asserted

Low

V

DDE

Low

Low

Asserted

High

V

DDE

Low

V

DD

Asserted

High

V

DDE

V

DD33

Low

Asserted

High impedance (Hi-Z)

V

DDE

V

DD33

V

DD

Asserted

Hi-Z

V

DDE

V

DD33

V

DD

Negated

Functional

Low

—

Asserted

Low

V

DDEH

Low

Asserted

High impedance (Hi-Z)

V

DDEH

V

DD

Asserted

Hi-Z

V

DDEH

V

DD

Negated

Functional