Freescale Semiconductor Demonstration Board for Freescale MC9S08SE8 DEMO9S08EL32AUTO DEMO9S08EL32AUTO Datenbogen

Freescale Semiconductor

117

 

Key features of the ICS module follow. For device specific information, refer to the ICS Characteristics in 
the Electricals section of the documentation.

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Frequency-locked loop (FLL) is trimmable for accuracy
— 0.2% resolution using internal 32kHz reference
— 2% deviation over voltage and temperature using internal 32kHz reference

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Internal or external reference clocks up to 5MHz can be used to control the FLL
— 3 bit select for reference divider is provided

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Internal reference clock has 9 trim bits available

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Internal or external reference clocks can be selected as the clock source for the MCU

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Whichever clock is selected as the source can be divided down
— 2 bit select for clock divider is provided

– Allowable dividers are: 1, 2, 4, 8
– BDC clock is provided as a constant divide by 2 of the DCO output

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Control signals for a low power oscillator as the external reference clock are provided
— HGO, RANGE, EREFS, ERCLKEN, EREFSTEN

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FLL Engaged Internal mode is automatically selected out of reset