Freescale Semiconductor Demonstration Board for Freescale MC9S08SE8 DEMO9S08EL32AUTO DEMO9S08EL32AUTO Datenbogen

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Freescale Semiconductor

 

7

CHnF

Channel n flag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs 
on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF 
is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. When 
channel n is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or 100%, CHnF will not 
be set even when the value in the TPM counter registers matches the value in the TPM channel n value registers.

A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by 
reading TPMxCnSC while CHnF is set and then writing a logic 0 to CHnF. If another interrupt request occurs 
before the clearing sequence is complete, the sequence is reset so CHnF remains set after the clear sequence 
completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost due to clearing a previous 
CHnF.

Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect.
0 No input capture or output compare event occurred on channel n
1 Input capture or output compare event on channel n

6

CHnIE

Channel n interrupt enable. This read/write bit enables interrupts from channel n. Reset clears CHnIE.
0 Channel n interrupt requests disabled (use for software polling)
1 Channel n interrupt requests enabled

5

MSnB

Mode select B for TPM channel n. When CPWMS=0, MSnB=1 configures TPM channel n for edge-aligned PWM 
mode. Refer to the summary of channel mode and setup controls in 

4

MSnA

Mode select A for TPM channel n. When CPWMS=0 and MSnB=0, MSnA configures TPM channel n for 
input-capture mode or output compare mode. Refer to 

 for a summary of channel mode and setup 

controls.
Note: If the associated port pin is not stable for at least two bus clock cycles before changing to input capture 

mode, it is possible to get an unexpected indication of an edge trigger.

3–2

ELSnB
ELSnA

Edge/level select bits. Depending upon the operating mode for the timer channel as set by CPWMS:MSnB:MSnA 
and shown in 

, these bits select the polarity of the input edge that triggers an input capture event, select 

the level that will be driven in response to an output compare match, or select the polarity of the PWM output.

Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general purpose I/O pin not related to any timer 
functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin 
available as a general purpose I/O pin when the associated timer channel is set up as a software timer that does 
not require the use of a pin.

X

XX

00

Pin not used for TPM - revert to general 

purpose I/O or other peripheral control