Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT Datenbogen
Produktcode
TWR-S12GN32-KIT
192 KByte Flash Module (S12FTMRG192K2V1)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
1097
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
executing (CCIF=0).
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R
FDIVLD
FDIVLCK
FDIV[5:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 30-5. Flash Clock Divider Register (FCLKDIV)
Table 30-7. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
6
FDIVLCK
Clock Divider Locked
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
restore writability to the FDIV field in normal mode.
5–0
FDIV[5:0]
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
during Flash program and erase algorithms.
during Flash program and erase algorithms.
shows recommended values for FDIV[5:0] based on the
BUSCLK frequency. Please refer to
,
”
for more information.