Freescale Semiconductor TWR-S12G64 Scalable Platform for Automotive Applications TWR-S12G64-KIT TWR-S12G64-KIT Datenbogen
Produktcode
TWR-S12G64-KIT
S12S Debug Module (S12SDBGV2)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
317
8.3.2
Register Descriptions
This section consists of the DBG control and trace buffer register descriptions in address order. Each
comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F
in the DBG module register address map. When ARM is set in DBGC1, the only bits in the DBG module
registers that can be written are ARM, TRIG, and COMRV[1:0].
comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F
in the DBG module register address map. When ARM is set in DBGC1, the only bits in the DBG module
registers that can be written are ARM, TRIG, and COMRV[1:0].
8.3.2.1
Debug Control Register 1 (DBGC1)
Read: Anytime
Write: Bits 7, 1, 0 anytime
Bit 6 can be written anytime but always reads back as 0.
Bits 4:3 anytime DBG is not armed.
Bit 6 can be written anytime but always reads back as 0.
Bits 4:3 anytime DBG is not armed.
NOTE
When disarming the DBG by clearing ARM with software, the contents of
bits[4:3] are not affected by the write, since up until the write operation,
ARM = 1 preventing these bits from being written. These bits must be
cleared using a second write if required.
bits[4:3] are not affected by the write, since up until the write operation,
ARM = 1 preventing these bits from being written. These bits must be
cleared using a second write if required.
0x002C
DBGADH
R
Bit 15
14
13
12
11
10
9
Bit 8
W
0x002D
DBGADL
R
Bit 7
6
5
4
3
2
1
Bit 0
W
0x002E
DBGADHM
R
Bit 15
14
13
12
11
10
9
Bit 8
W
0x002F
DBGADLM
R
Bit 7
6
5
4
3
2
1
Bit 0
W
1
This bit is visible at DBGCNT[7] and DBGSR[7]
2
This represents the contents if the Comparator A control register is blended into this address.
3
This represents the contents if the Comparator B control register is blended into this address
4
This represents the contents if the Comparator C control register is blended into this address
Address: 0x0020
7
6
5
4
3
2
1
0
R
ARM
0
0
BDM
DBGBRK
0
COMRV
W
TRIG
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-3. Debug Control Register (DBGC1)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
Figure 8-2. Quick Reference to DBG Registers