Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
MSC8156 Reference Manual, Rev. 2
25-50
Freescale
Semiconductor
Debugging, Profiling, and Performance Monitoring
25.2.13.13 DPU Counter A2 Value Registers (DP_CA2V)
DP_CA2V is a 32-bit register containing the specified counter value.
bit fields.
25.2.13.14 DPU Counter B0 Control Register (DP_CB0C)
The DP_CB0C is a 32-bit register that controls the operation of the DPU Extension Support Counter B0,
including what events and when they are counted.
including what events and when they are counted.
Table 25-28 defines the DP_CB0C bit fields.
DP_CA2V
DPU Counter A2 Value Registers
Offset 0x40
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
—
CV
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CV
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 25-25. DP_CA2V Bit Descriptions
Name
Reset
Description
Settings
—
31
0
Reserved. Write to zero for future compatibility.
CV
30–0
0
Counter Value
Stores the value of the counter.
Stores the value of the counter.
DP_CB0C
DPU Counter B0 Control Register
Offset 0x54
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
—
CDMP
CDM
—
CENMP
CENM
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
CEP
—
CE
—
CMODE
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 25-26. DP_CB0C Bit Descriptions
Name
Reset
Description
Settings
—
31–30
0
Reserved. Write to zero for future compatibility.