Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch

Freescale Semiconductor

 

5-15

Table 5-6 defines the combined External and Hard Coded Reset Configuration Word High field 
values. 

When the MSC8156 device is configured not to load the RCW from I

2

C EEPROM or external 

pins, it can be initialized using one of the two hard-coded default options listed in Table 5-7 and 
Table 5-8.

Table 5-7 defines the Hard Coded Reset Configuration Word Low field values.

Table 5-6.  Combined External and Hard Coded Reset Configuration Word High Field Values

31–30

—

00

Reserved. Should be cleared.

29

EWDT

0

Disable Watch Dog Timers.

28

PRDY

0

PCI Express not ready.

27–24

BPRT

0, RC[9–7]

See for details Table 5-10.

23

RIO

1

RapidIO access enabled.

22

RPT

RC6

RapidIO pass-through enable bit.

21

RHE

0

RapidIO host mode disabled.

20–19

—

00

Reserved. Should be cleared.

18

RM

0

Not reset master.

17

BP

0

Boot patch disabled.

16–13

—

00000

Reserved. Should be cleared.

12

GE1

RC5

0 - TDM2 and TDM3 are driven on pins.
1 - RGMII of GE1 is driven on pins.

11

GE2

RC4

0 - TDM0 and TDM1 are driven on pins.
1 - RGMII of GE2 is driven on pins.

10

R1A

0

SerDes Port 1 RapidIO interface does not accept all.

9

R2A

0

SerDes Port 2 RapidIO interface does not accept all.

8–3

DEVID

00, RC[3–0]

DEVID[5–4] = 00, DEVID[3–0] = RC[3–0]

2

—

0

Reserved. Should be cleared.

1

RMU

0

RMU access local memory on internal port number 0

0

CTLS

1

Common transport type is Large System.

Table 5-7.   Hard Coded Reset Configuration Word Low Field Values

31–30

CLKO

00

Select PLL0 divided output clock to be driven on CLKO

29

—

0

Reserved. Should be cleared.