Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
MSC8156 Reference Manual, Rev. 2
12-106
Freescale
Semiconductor
DDR SDRAM Memory Controller
12.8.34
DDR SDRAM Memory Data Path Error Injection Mask High Register
(MnDATA_ERR_INJECT_HI)
(MnDATA_ERR_INJECT_HI)
DATA_ERR_INJECT_HI register is used to inject ECC errors for the 32-msb of a 64-bit
SDRAM data bus interfaces.
SDRAM data bus interfaces.
12.8.35
DDR SDRAM Memory Data Path Error Injection Mask Low Register
(MnDATA_ERR_INJECT_LO)
(MnDATA_ERR_INJECT_LO)
—
15–8
0
Reserved. Always read as zero
IP_CFG
7–0
0
IP Block Configuration Options
DATA_ERR_INJECT_HI
DDR SDRAM Memory Data Path
Offset 0x0E00
Error Injection Mask High Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
EIMH
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EIMH
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 12-55. DATA_ERR_INJECT_HI Bit Descriptions
Bit Reset
Description
EIMH
31–0
0
Error Injection Mask High Data Path
Tests ECC by forcing errors on the highest 32 bits of the data path. When error injection is
enabled, setting a bit causes the corresponding data path bit to be inverted during memory bus
writes.
Tests ECC by forcing errors on the highest 32 bits of the data path. When error injection is
enabled, setting a bit causes the corresponding data path bit to be inverted during memory bus
writes.
DATA_ERR_INJECT_LO
DDR SDRAM Memory Data Path
Offset 0x0E04
Error Injection Mask Low Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
EIML
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EIML
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 12-54. DDR_IP_REV2 Bit Descriptions (Continued)
Bit Reset
Description