Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch

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MSC8156  Reference Manual, Rev. 2
14-28
  
Freescale Semiconductor
Direct Memory Access (DMA) Controller
14.7.1
DMA Buffer Descriptor Base Registers x (DMABDBRx)
Each DMABDBRx holds the user-programmable addresses of the BD tables for DMA channel x. 
There are two fields: BDTPTR that identifies the base address of the Buffer Descriptor Table and 
DESO field that identifies the location offset for the destination buffer within the table. All the 
channel properties should be programmed, including the relevant BD, before the channel is 
enabled. For more information on BD address calculation, see the discussion in 
Section 14.7.22DMA Channel Buffer Descriptors, on page 14-45.
DMABDBR[0–15]
DMA Buffer Descriptor Base Registers 0–15
Offset 0x000 + x*0x4
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BDTPTR
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BDTPTR
DESO
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 14-15.  DMABDBRx Field Descriptions
Bits
Reset
Description
Setting
31–28
0
Reserved. Write to zero for future compatibility.
BDTPTR
27–4
0
Buffer Descriptor Table Pointer
Holds the 24 most significant bits, out of the 32 
bit Buffer Descriptors Table (BDT) address.
DESO
3–0
0
Destination Offset
Holds the offset of destination buffer descriptor 
table from the BTD base (BDTPTR 
×
 256).
0000
Destination table offset is 0x20.
0001
Destination table offset is 0x40.
0010  Destination table offset is 0x80.
0011  Destination table offset is 0x100.
0100  Destination table offset is 0x200.
0101  Destination table offset is 0x400.
0110  Destination table offset is 0x600.
0111 
Destination table offset is 0x800.
1000  Destination table offset is 0x1000.
1001  Destination table offset is 0x2000.
1010  Destination table offset is 0x3000.
1011  Destination table offset is 0x4000.
11xx Reserved.