Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
MSC8156
Reference Manual, Rev. 2
15-2
Freescale
Semiconductor
High Speed Serial Interface (HSSI) Subsystem
This chapter includes the interface component programming model, with the exception of the
SerDes multiplexing programming, which is done using the S1P and S2P bits in the low half of
the reset configuration word (RCW), as described in Chapter 5, Reset. The communication
controllers supported within the block are described in Chapter 16, Serial RapidIO Controller
and Chapter 17, PCI Express Controller. While the SGMII lines are multiplexed through the
SerDes interfaces, they are functionally part of the QUICC Engine subsystem, as described in
Chapter 18, QUICC Engine Subsystem.
SerDes multiplexing programming, which is done using the S1P and S2P bits in the low half of
the reset configuration word (RCW), as described in Chapter 5, Reset. The communication
controllers supported within the block are described in Chapter 16, Serial RapidIO Controller
and Chapter 17, PCI Express Controller. While the SGMII lines are multiplexed through the
SerDes interfaces, they are functionally part of the QUICC Engine subsystem, as described in
Chapter 18, QUICC Engine Subsystem.
15.1
HSSI Subsystem Block Diagram
Figure 15-1 shows a block diagram of the HSSI.
Figure 15-1. HSSI Block Diagram
OCN Fabric
Port1
Port 3
Port 2
Port 6
Port 5
Port 4
Port 0
Port 7
RMU
SRIO0
SRIO1
PCI Express
PCI Express
to OCN Bridge
SerDes2
PHY2
PHY1
SerDes1
OCNDMA0
DMA to OCN
Bridge
OCNDMA1
DMA to OCN
Bridge
OCN to MBus
Bridge 0
OCN to MBus
Bridge 1
HSSI to MBus Bridge
Serial RapidIO x1/x4 Interface
x1/x2/x4 PCI-Express
Serial RapidIO x1/x4 Interface
Two SGMII
QUICC En
gin
e
Su
bs
y
s
tem
HSSI
QUICC En
gin
e
e
Su
bs
y
y
s
tem
Two SGMII
Notes: 1.
The actual signals multiplexed for each PHY is determined by the SerDes configuration field contents in the lower
32 bits of the reset configuration word, which are recorded in RCWLR[S1P] and RCWLR[S2P]. See Chapter 5,
Reset for details.
32 bits of the reset configuration word, which are recorded in RCWLR[S1P] and RCWLR[S2P]. See Chapter 5,
Reset for details.
2.
You must distribute the access loading between O2M0 (Port 1) and O2M1 (Port 5) for optimal performance.
Although the internal OCN arbiters attempt to balance access automatically, these ports can be configured to
work specifically with individual RapidIO inbound windows (see Section 16.6.58 for details) and PCI Express
inbound windows (see Section 17.4.1.4.13 for details).
Although the internal OCN arbiters attempt to balance access automatically, these ports can be configured to
work specifically with individual RapidIO inbound windows (see Section 16.6.58 for details) and PCI Express
inbound windows (see Section 17.4.1.4.13 for details).