Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
Programming Model
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
17-39
17.4.1.2.7
PCI Express Link Speed Control Register (PEX_LSCR)
The PCI Express link speed control register, shown in Figure 17-23, provides software a
mechanism to dynamically changing the link speed.
mechanism to dynamically changing the link speed.
The fields of the PCI Express link speed control register are described in Table 17-28.
Offset 0x108
Access: Read/Write
31
16 15
12 11
5
4
3
2
1
0
R
—
LSRS
—
LSA
—
LSM LSR
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n
n
n
n
0
0
0
0
0
0
0
0
0
0
n
0
Figure 17-23. PCI Express Link Speed Control Register (PEX_LSCR)
Table 17-28. PEX_LSCR Field Descriptions
Bits
Name
Description
31–16
—
Reserved
15-12
LSRS
Link speed request size. These bits indicate the size of the link speed request. Software should first
determine the link partner’s speed by reading PEX_LSSR[LPAS] bits before initializing these bits.
0001 - 2.5 Gb/s speed
0010 - 5.0 Gb/s speed
All other encodings are reserved and should not be used.
determine the link partner’s speed by reading PEX_LSSR[LPAS] bits before initializing these bits.
0001 - 2.5 Gb/s speed
0010 - 5.0 Gb/s speed
All other encodings are reserved and should not be used.
11–5
—
Reserved
4
LSA
Link speed auto. This bit is set by software. It is gated with the Hardware Autonomous Speed Disable bit.
3-2
—
Reserved
1
LSM
Link speed mask. This bit when set indicates that 5.0 Gb/s speed is not supported.
0
LSR
Link speed request. This bit when set by software will initiate a change in link speed as indicated by LSRS.
Once the link speed operation finishes, this bit is cleared by hardware.
Once the link speed operation finishes, this bit is cleared by hardware.