Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
Programming Model
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
17-45
17.4.1.4.5
PCI Express Outbound Window Attributes Registers (PEXOWARn)
The PCI Express outbound window attributes registers, shown in Figure 17-31 and Figure
17-32, define the window sizes to translate and other attributes for the translations. 64 Gbytes is
the largest window size allowed. Figure 17-31 shows the outbound window attributes register 0
(PEXOWAR0).
17-32, define the window sizes to translate and other attributes for the translations. 64 Gbytes is
the largest window size allowed. Figure 17-31 shows the outbound window attributes register 0
(PEXOWAR0).
Figure 17-32 shows the PCI Express outbound window attributes registers 1–4 (PEXOWARn).
Table 17-35 describes the fields of the PCI Express outbound window attributes registers.
Offset 0xC10
Access: Mixed
31
30
29
28
27
26 25 24 23 22 21
20
19 18 17 16
15
12
11
6
5
0
R EN
ROE NS
—
TC
—
RTT
WTT
—
OWS
W
Reset 1
0
0
0
0
0 0 0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
Figure 17-31. PCI Express Outbound Window Attributes Register 0 (PEXOWAR0)
Offset Window 1: 0xC30
Window 2: 0xC50
Window 3: 0xC70
Window 4: 0xC90
Window 3: 0xC70
Window 4: 0xC90
Access: Read/Write
31
30
29
28
27
26
24
23
21
20
19
16
15
12
11
6
5
0
R
EN
ROE NS
TC
RTT
WTT
—
OWS
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0 0 0 0 0 0
1
0
0
0
1
1
Figure 17-32. PCI Express Outbound Window Attributes Registers 1–4 (PEXOWARn)
Table 17-35. PEXOWARn Field Descriptions
Bits
Name
Description
31
EN
Enable. This bit enables this address translation window. For the default window, this bit is read-only and
always hardwired to 1.
0 Disable outbound translation window
1 Enable outbound translation window
always hardwired to 1.
0 Disable outbound translation window
1 Enable outbound translation window
30–29
—
Reserved
28
ROE
Relaxed ordering enable. This bit when set and the PCI Express device control register[Enable Relaxed] bit
is set will enable the Relaxed Ordering bit for the packet. This bit only applies to memory transactions.
0 Default ordering
1 Relaxed ordering
is set will enable the Relaxed Ordering bit for the packet. This bit only applies to memory transactions.
0 Default ordering
1 Relaxed ordering
27
NS
No snoop enable. This bit when set and the PCI Express device control register[Enable No Snoop] bit is set
will enable the no snoop bit for the packet. This bit only applies to memory transactions.
0 Snoopable
1 No snoop
will enable the no snoop bit for the packet. This bit only applies to memory transactions.
0 Snoopable
1 No snoop
26–24
—
Reserved