Analog Devices AD1955 Evaluation Board EVAL-AD1955EBZ EVAL-AD1955EBZ Datenbogen
Produktcode
EVAL-AD1955EBZ
REV. 0
–4–
AD1955
SPECIFICATIONS
(continued)
GROUP DELAY
Chip Mode
Group Delay Calculation
f
S
(kHz)
Group Delay
Unit
INT8
Mode
5553/(128
f
S
)
48
903.8
µs
INT4
Mode
5601/(64
f
S
)
96
911.6
µs
INT2
Mode
5659/(32
f
S
)
192
921
µs
Specifications subject to change without notice.
DIGITAL TIMING
(Guaranteed over –40
C to +85C, AVDD = DVDD = 5.0 V 10%.)
Parameter
Description
Min
Unit
t
DMP
MCLK Period (F
MCLK
= 256
F
LRCLK
)
50
ns
t
DML
MCLK LO Pulsewidth (All Modes)
0.4
t
DMP
ns
t
DMH
MCLK HI Pulsewidth (All Modes)
0.4
t
DMP
ns
t
DBH
BCLK/EF_BCLK High
20
ns
t
DBL
BCLK/EF_BCLK Low
20
ns
t
DBP
BCLK/EF_BCLK Period
60
ns
t
DLS
LRCLK/EF_WCLK Setup
0
ns
t
DLH
LRCLK Hold (DSP Serial Port Mode Only)
15
ns
t
DWH
EF_WCLK High
20
ns
t
DWL
EF_WCLK Low
20
ns
t
DDS
SDATA/EF_LDATA/EF_RDATA Setup
0
ns
t
DDH
SDATA/EF_LDATA/EF_RDATA Hold
20
ns
t
DPHS
DSD_PHASE Setup
20
ns
t
DSDS
DSD_DATA Setup
5
ns
t
DSDH
DSD_DATA Hold
5
ns
t
DSKP
DSD_SCLK Period
60
ns
t
DSKH
DSD_SCLK High
20
ns
t
DSKL
DSD_SCLK Low
20
ns
t
DMP
CCLK Period
50
ns
t
DML
CCLK LO Pulsewidth
15
ns
t
DMH
CCLK HI Pulsewidth
10
ns
t
CLS
CLATCH Setup
0
ns
t
CLH
CLATCH Hold
15
ns
t
CDS
CDATA Setup
0
ns
t
CDH
CDATA Hold
5
ns
t
RSTL
RST LO Pulsewidth
10
ns
Specifications subject to change without notice.