Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen

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AT91SAM9M10-G45-EK
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SAM9M10 [SUMMARY]
6355ES–ATARM–12-Mar-13
 
z
USB Device High Speed and Host EHCI High Speed operations are NOT allowed
z
Full Speed OHCI input clock is PLLACK, USBDIV is 7 (division by 8)
z
System Input clock is PLLACK, PCK is 384 MHz
z
MDIV is ‘11’, MCK is 128 MHz
z
DDR2 can be used at up to 128 MHz
8.8
Periodic Interval Timer
z
Includes a 20-bit Periodic Counter, with less than 1
μs accuracy
z
Includes a 12-bit Interval Overlay Counter
z
Real Time OS or Linux/WinCE compliant tick generator
8.9
Watchdog Timer
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16-bit key-protected only-once-Programmable Counter
z
Windowed, prevents the processor to be in a dead-lock on the watchdog access
8.10
Real-Time Timer
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Real-Time Timer, allowing backup of time with different accuracies
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32-bit Free-running back-up Counter 
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Integrates a 16-bit programmable prescaler running on slow clock 
z
Alarm Register capable to generate a wake-up of the system through the Shut Down Controller
8.11
Real Time Clock
z
Low power consumption 
z
Full asynchronous design
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Two hundred year calendar
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Programmable Periodic Interrupt 
z
Alarm and update parallel load
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Control of alarm and update Time/Calendar Data In
8.12
General-Purpose Backup Registers
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Four 32-bit backup general-purpose registers
8.13
Advanced Interrupt Controller
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Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
z
Thirty-two individually maskable and vectored interrupt sources
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Source 0 is reserved for the Fast Interrupt Input (FIQ)
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Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
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Programmable Edge-triggered or Level-sensitive Internal Sources
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Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
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One External Sources plus the Fast Interrupt signal
z
8-level Priority Controller
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Drives the Normal Interrupt of the processor
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Handles priority of the interrupt sources 1 to 31
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Higher priority interrupts can be served during service of lower priority interrupt
z
Vectoring
z
Optimizes Interrupt Service Routine Branch and Execution