Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Datenbogen

32099G–06/2011

USART in SPI Master Mode With (CPOL= CPHA= 0) or (CPOL= CPHA= 1)

USART in SPI Master Mode With (CPOL= 0 and CPHA= 1) or (CPOL= 1 and 
CPHA= 0)

Notes:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

2. Where: 

USPI0

USPI1

MISO

SPCK

MOSI

USPI2

USPI3

USPI4

MISO

SPCK

MOSI

USPI5

USART in SPI Mode Timing, Master Mode

USPI0

MISO setup time before SPCK rises

V

VDDIO 

from 

3.0V to 3.6V, 

maximum 

external 

capacitor = 

40pF

30.0+ t

SAMPLE

ns

USPI1

MISO hold time after SPCK rises

0

USPI2

SPCK rising to MOSI delay

8.5

USPI3

MISO setup time before SPCK falls

25.5 + t

SAMPLE

USPI4

MISO hold time after SPCK falls

0

USPI5

SPCK falling to MOSI delay

13.6

2

×

------------------------------------

1
2

---

⎝

⎠

⎛

⎞ t

×

–

=