Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Datenbogen
Produktcode
AT91SAM9N12-EK
Preface
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
xvii
Read this chapter for a description of the Bus Interface Unit (BIU)
interface to AMBA.
interface to AMBA.
Read this chapter for a description of how speculative noncachable
instruction fetches are used in the ARM926EJ-S processor to improve
performance.
instruction fetches are used in the ARM926EJ-S processor to improve
performance.
Read this chapter for a description of the coprocessor interface. The
chapter includes timing diagrams for coprocessor operations.
chapter includes timing diagrams for coprocessor operations.
Read this chapter for the Instruction Memory Barrier (IMB) description
and how IMB operations are used to ensure consistency between data and
instruction streams processed by the ARM926EJ-S processor.
and how IMB operations are used to ensure consistency between data and
instruction streams processed by the ARM926EJ-S processor.
Read this chapter to understand how Embedded Trace Macrocell (ETM)
is supported in the ARM926EJ-S processor.
is supported in the ARM926EJ-S processor.
Read this chapter for a description of the debug interface and
EmbeddedICE-RT.
EmbeddedICE-RT.
Read this chapter for a description of the power management facilities
provided by the ARM926EJ-S processor.
provided by the ARM926EJ-S processor.
This appendix lists the ARM926EJ-S processor signals in functional
groups.
groups.
Read this appendix for detailed information on the registers used for test
and debug.
and debug.