Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Datenbogen

ARM DDI0198D

B-17

Figure B-10 shows the flow and precedence of CP15 c15 control bits in resolving the 
cachable and bufferable attributes of a memory reference.

MMU

Memory

region

remapping

NCNB

NCB

CNB (write-through)

CB (write-back)

NCNB

NCB

CNB (write-through)

CB (write-back)

Force

NCB store

to be

NCNB

MDDEB bit:

MMU disabled,

DCache enabled

Memory Region Remap Register

Debug Override Register

Page table descriptor

FNCB bit:

Force NCB store

to be NCNB

C and B bits

M, C, and I bits

Control Register