Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Datenbogen

Atmel

Produktcode

AT91SAM9N12-EK

Contents

iv

Copyright © 2001-2003 ARM Limited. All rights reserved.

ARM DDI0198D

Caches and Write Buffer

About the caches and write buffer .............................................................. 4-2

Write buffer ................................................................................................. 4-4

Enabling the caches ................................................................................... 4-5

TCM and cache access priorities ............................................................... 4-8

Cache MVA and Set/Way formats .............................................................. 4-9

Tightly-Coupled Memory Interface

About the tightly-coupled memory interface ............................................... 5-2

TCM interface signals ................................................................................. 5-4

TCM interface bus cycle types and timing .................................................. 5-8

TCM programmer’s model ........................................................................ 5-19

TCM interface examples ........................................................................... 5-20

TCM access penalties .............................................................................. 5-29

TCM write buffer ....................................................................................... 5-30

Using synchronous SRAM as TCM memory ............................................ 5-31

TCM clock gating ...................................................................................... 5-32

Bus Interface Unit

About the bus interface unit ........................................................................ 6-2

Supported AHB transfers ............................................................................ 6-3

Noncachable Instruction Fetches

About noncachable instruction fetches ....................................................... 7-2

Coprocessor Interface

About the ARM926EJ-S external coprocessor interface ............................ 8-2

LDC/STC .................................................................................................... 8-4

MCR/MRC .................................................................................................. 8-6

CDP ............................................................................................................ 8-8

Privileged instructions ................................................................................. 8-9

Busy-waiting and interrupts ...................................................................... 8-10

CPBURST ................................................................................................ 8-11

CPABORT ................................................................................................ 8-12

nCPINSTRVALID ..................................................................................... 8-13

Connecting multiple external coprocessors .............................................. 8-14

Instruction Memory Barrier

About the instruction memory barrier operation ......................................... 9-2

IMB operation ............................................................................................. 9-3

Example IMB sequences ............................................................................ 9-5

Embedded Trace Macrocell Support

About Embedded Trace Macrocell support .............................................. 10-2