Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Datenbogen
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Produktcode
AT91SAM9N12-EK
1032
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
46.5.6 SHA Interrupt Status Register
Name: SHA_ISR
Address:
0xF001401C
Access:
Read-only
• DATRDY: Data Ready
0: Output data is not valid.
1: 512-bit block process is completed.
DATRDY is cleared when a Manual process occurs (START bit in SHA_CR) or when a software triggered hardware reset of the
SHA interface is performed (SWRST bit in SHA_CR).
SHA interface is performed (SWRST bit in SHA_CR).
• URAD: Unspecified Register Access Detection Status
0: No unspecified register access has been detected since the last SWRST.
1: At least one unspecified register access has been detected since the last SWRST.
URAD bit is reset only by the SWRST bit in the SHA_CR control register.
URAT field indicates the unspecified access type.
• URAT: Unspecified Register Access Type
Only the last Unspecified Register Access Type is available through the URAT field.
URAT field is reset only by the SWRST bit in the SHA_CR control register.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
URAT
–
–
–
URAD
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
DATRDY
Value
Description
0x0
Input Data Register 0 to 15 written during the data processing in DMA mode. (URAD=0x1 and URAT=0x0 can
occur only if DUALBUFF is cleared in SHA_MR)
occur only if DUALBUFF is cleared in SHA_MR)
0x1
Output Data Register read during the data processing.
0x2
Mode Register written during the data processing.
0x3
Write-only register read access.