Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Datenbogen
Produktcode
AT91SAM9N12-EK
977
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
• MODE: LCD Controller Output Mode
• VSPSU: LCD Controller Vertical Synchronization Pulse Setup Configuration
0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge.
1: The vertical synchronization pulse is asserted one pixel clock cycle before the horizontal pulse.
• VSPHO: LCD Controller Vertical Synchronization Pulse Hold Configuration
0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge.
1: The vertical synchronization pulse is held active one pixel clock cycle after the horizontal pulse.
• GUARDTIME: LCD DISPLAY Guard Time
Number of frames inserted during start up before LCD_DISP assertion.
Number of frames inserted after LCD_DISP reset.
Value
Name
Description
0
OUTPUT_12BPP
LCD output mode is set to 12 bits per pixel
1
OUTPUT_16BPP
LCD output mode is set to 16 bits per pixel
2
OUTPUT_18BPP
LCD output mode is set to 18 bits per pixel
3
OUTPUT_24BPP
LCD output mode is set to 24 bits per pixel