Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen

 123

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

 SHDW_MR

0xFFFFFD14

 Read/Write 

 

Defines the number of 16 Slow Clock cycles, the level detection on the corresponding input pin shall last before the wake-
up event occurs. Because of the internal synchronization of WKUP0, the 

SHDN

 pin is released 

(CPTWK x 16 + 1) Slow Clock cycles after the event on WKUP.

0 = The RTT Alarm signal has no effect on the Shutdown Controller.

1 = The RTT Alarm signal forces the de-assertion of the SHDN pin.

0 = The RTC Alarm signal has no effect on the Shutdown Controller.

1 = The RTC Alarm signal forces the de-assertion of the SHDN pin.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

RTCWKEN

RTTWKEN

15

14

13

12

11

10

9

8

–

–

–

–

7

6

5

4

3

2

1

0

CPTWK0

–

–

WKMODE0

0

0

None. No detection is performed on the wake-up input

0

1

Low to high level

1

0

High to low level

1

1

Both levels change