Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen
Produktcode
AT91SAM9M10-G45-EK
1324
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
47.15.5.2
Timing Constraints
The Ethernet controller must satisfy the timings of MAX corner standards given in
Notes:
1. For EMAC output signals, Min and Max access time are defined. The Min access time is the time between the EDMC falling
edge and the signal change. The Max access time is the time between the EDMC falling edge and the signal stabilization.
illustrates Min and Max accesses for EMAC3.
Figure 47-20.
Min and Max Access Time of EMAC Output Signals
47.15.5.3
MII Mode
Table 47-42.
EMAC Signals Relative to EMDC
Symbol
Parameter
Min (ns)
Max (ns)
EMAC
1
Setup for EMDIO from EMDC rising
13.5
EMAC
2
Hold for EMDIO from EMDC rising
10
EMAC
3
EMDIO toggling from EMDC falling
0
2
EMDC
EMDIO
EMAC
3 max
EMAC
1
EMAC
2
EMAC
4
EMAC
5
EMAC
3 min
Table 47-43.
EMAC MII Specific Signals
Symbol
Parameter
Min (ns)
Max (ns)
EMAC
4
Setup for ECOL from ETXCK rising
10
EMAC
5
Hold for ECOL from ETXCK rising
10
EMAC
6
Setup for ECRS from ETXCK rising
10
EMAC
7
Hold for ECRS from ETXCK rising
10
EMAC
8
ETXER toggling from ETXCK rising
3
25
EMAC
9
ETXEN toggling from ETXCK rising
4.7
25
EMAC
10
ETX toggling from ETXCK rising
3
25
EMAC
11
Setup for ERX from ERXCK
10
EMAC
12
Hold for ERX from ERXCK
10
EMAC
13
Setup for ERXER from ERXCK
10
EMAC
14
Hold for ERXER from ERXCK
10
EMAC
15
Setup for ERXDV from ERXCK
10
EMAC
16
Hold for ERXDV from ERXCK
10