Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen

 188

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

1.

NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling 
edge. 

2.

NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge;

3.

NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.

The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on
the address bus to the point where address may change. The total read cycle time is equal to:

NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD 

= NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD

All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles.
To ensure that the NRD and NCS timings are coherent, user must define the total read cycle instead of the hold
timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as:

NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE 

NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE

If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously
in case of consecutive read cycles in the same memory (see 

No Setup, No Hold On NRD and NCS Read Signals

MCK

NRD_PULSE

NCS_RD_PULSE

NRD_CYCLE

NRD_PULSE

NRD_PULSE

NCS_RD_PULSE

NCS_RD_PULSE

NRD_CYCLE

NRD_CYCLE

A[25:2]

NBS0,NBS1,
NBS2,NBS3,
A0, A1

NCS

NRD

D[31:0]