Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

 DDRSDRC Module Diagram 

• An Interconnect-Matrix that manages concurrent accesses on the AHB bus between four AHB masters and 

integrates an arbiter.

• A controller that translates AHB requests (Read/Write) in the SDRAM protocol.

Memory Controller

Finite State Machine

SDRAM Signal Management

Addr, DQM

Data

Asynchronous Timing
Refresh Management

DDR-SDR

Devices

Power Management

DQS

ras,cas,we
cke

clk/nclk

odt

DDR-SDR Controller

Interconnect Matrix

Input

Stage

Input

Stage

Input

Stage

Output 

Stage

Arbiter

APB

AHB  Slave Interface 0

AHB  Slave Interface 1

AHB  Slave Interface 2

AHB  Slave Interface 3

Input

Stage

Interface  APB